Aisin and Tohoku University Develop Embedded MRAM AI Chip Claiming Significant Power Reduction
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Japanese auto parts maker Aisin and Tohoku University have developed a new edge AI chip featuring embedded MRAM. Media reports state the architecture eliminates external DRAM and SSDs, with Aisin claiming a roughly 98% power reduction compared to conventional chips alongside reduced detection latency. The design targets edge AI and automotive cameras, though mass production schedules and automotive qualification details remain unannounced.
Japanese automotive supplier Aisin, in collaboration with Tohoku University, has developed an edge AI chip featuring embedded MRAM. According to reports from Nikkei Asia and The Nikkei, the architecture leverages MRAM's non-volatile, high-speed characteristics to eliminate the external DRAM and SSDs required by conventional SoCs. Aisin claims this design cuts power consumption to one-fiftieth of comparable chips (a reduction of roughly 98%) and reduces processing time for tasks like object detection to one-tenth. The research builds upon a 16nm prototype previously unveiled under NEDO in July 2025; however, reports do not clarify whether current claims stem from that prototype or new test conditions. No commercial mass production schedules, cost details, or automotive reliability validations have been disclosed.
Key takeaways
- Aisin and Tohoku University developed an AI chip architecture with embedded MRAM, eliminating external DRAM and SSDs to boost energy efficiency.
- Media reports cite Aisin claiming a power reduction to one-fiftieth (about 98%) and a tenfold decrease in object detection processing time.
- The development builds on a July 2025 16nm prototype under NEDO, though reports omit whether new silicon or test conditions were used.
- No production schedules, automotive-grade qualification results, or client engagements have been made public so far.
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