Pat Gelsinger Calls for 10,000x AI Efficiency Boost as Playground Showcases Hardware Startups in Taiwan

At a press conference held in Taiwan, Pat Gelsinger, partner at deep-tech venture firm Playground Global, asserted that physical resources such as power, memory, and fab capacity cannot expand without limit to support future AI demand, making a 10,000-fold increase in computing efficiency necessary. Playground showcased several portfolio startups tackling hardware bottlenecks: Nagare Labs with its 2T0C Z2RAM architecture aiming for 300 mm wafer fabrication; Powerlattice demonstrating an integrated voltage regulator chiplet designed to cut compute power consumption by over 50%; Syenta displaying localized electrochemical manufacturing for interconnects; and Ayar Labs utilizing optical interconnects while officially opening a Hsinchu office to collaborate with Taiwan's manufacturing ecosystem.

Key takeaways

• Pat Gelsinger stated in Taiwan that AI computing efficiency must rise by at least 10,000 times, as incremental improvements cannot meet future physical resource constraints.
• Nagare Labs is developing 2T0C Z2RAM stacked on logic chips, backed by $5 million in seed funding and planning to advance to 300 mm wafer manufacturing.
• Powerlattice demonstrated an integrated voltage regulator chiplet and claimed the architecture could reduce compute power consumption by over 50%.
• Ayar Labs introduced optical interconnect solutions and launched its Hsinchu office with a 10-person team to deepen ties with Taiwan's foundries and system makers.